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74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs
July 1996 Revised May 2005
74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is byte controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation.
Features
s Separate control logic for each nibble s 16-bit version of the ABT541 s Outputs sink capability of 64 mA, source capability of 32 mA s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT16541CSSC 74ABT16541CMTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names OE n I0-I15 O0-O15 Description Output Enable Inputs (Active Low) Inputs Outputs
(c) 2005 Fairchild Semiconductor Corporation
DS012149
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74ABT16541
Truth Tables
Inputs OE 1 L L H X OE 2 L L X H Inputs OE 4 L L H X
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Functional Description
Outputs I0-I7 L H X X O0-O7 L H Z Z Outputs I8-I15 L H X X O8-O15 L H Z Z The ABT16541 contains sixteen non-inverting buffers with 3-STATE outputs. The device is byte (8 bits) controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Logic Diagrams
OE 3 L L X H
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74ABT16541
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA)
65qC to 150qC 55qC to 125qC 55qC to 150qC 0.5V to 7.0V 0.5V to 7.0V 30 mA to 5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate ('V/'t) Data Input Enable Input 50 mV/ns 20 mV/ns
40qC to 85qC 4.5V to 5.5V
0.5V to 5.5V 0.5V to VCC
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 Min 2.0 0.8 Typ Max Units V V V V V V Min Min Min Min Max Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN IOH IOH IOL VIN VIN VIN VIN VIN IID
1.2
18 mA 3 mA 32 mA
64 mA 2.7V (Note 3) VCC 7.0V 0.5V (Note 3) 0.0V 1.9 PA
PA PA
1 1
PA
V
Max 0.0
All Other Pins Grounded IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs 3-STATE Outputs 3-STATE 10
PA PA
mA
0-5.5V 0-5.5V Max Max 0.0 Max Max Max
VOUT VOUT VOUT VOUT VOUT
2.7V; OEn 0.5V; OEn 0.0V VCC 5.5V
2.0V 2.0V
10 100 275
50 100 100 60 100 2.5 2.5 50
PA PA PA
mA
All Other Pins GND All Outputs HIGH All Outputs LOW OEn VI Max VCC VCC 2.1V VCC 2.1V VCC 2.1V
PA
mA mA
All Others at VCC or GND Enable Input VI Data Input VI
PA
mA/
All Others at VCC or GND ICCD Dynamic ICC (Note 3) VOLP VOLV VOHV VIHD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage 0.4 No Load 0.1 0.7 Outputs Open, OEn Max 5.0 5.0 5.0 5.0 One Bit Toggling, 50% Duty Cycle V V V V TA TA TA TA 25qC (Note 4) 25qC (Note 4) 25qC (Note 6) 25qC (Note 5) GND
MHz
1.3
2.7 2.0
1.0
3.0 1.4
3
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74ABT16541
DC Electrical Characteristics
Symbol VILD Parameter Maximum LOW Level Dynamic Input Voltage
(Continued)
VCC 5.0 TA
Min
Typ 1.2
Max 0.8
Units V
Conditions 25qC (Note 5)
Note 3: Guaranteed but not tested. Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested. Note 6: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
TA 25qC Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.0 1.5 1.5 1.0 1.0 VCC 5V CL 50 pF Typ 2.3 2.7 3.5 3.5 4.2 3.2 Max 3.4 3.9 5.2 6.0 5.1 5.1 TA
40qC to 85qC
4.5V-5.5V 50 pF Max 3.4 3.9 5.2 6.0 5.1 5.1 ns ns ns CL Units
VCC
Min 1.0 1.0 1.5 1.5 1.0 1.0
Extended AC Electrical Characteristics
40qC to 85qC
VCC Symbol Parameter CL 4.5V-5.5V 50 pF TA
40qC to 85qC
4.5V-5.5V 250 pF CL
TA
40qC to 85qC
4.5V-5.5V 250 pF Units CL
VCC
VCC
16 Outputs Switching (Note 7) Min fTOGGLE tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Toggle Frequency Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.5 1.5 1.5 1.5 1.0 1.0 Typ 100 5.0 5.3 6.5 6.5 6.7 6.7 Max
1 Output Switching (Note 8) Min 1.5 1.5 2.5 2.5 (Note 10) Max 6.0 6.0 7.8 7.8
16 Outputs Switching (Note 9) Min 2.5 2.5 2.5 2.5 (Note 10) Max MHz 8.0 8.0 9.5 8.5 ns ns ns
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 10: The 3-STATE delay times are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
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74ABT16541
Skew
TA
40qC to 85qC
4.5V-5.5V 50 pF CL
TA
40qC to 85qC
4.5V-5.5V 250 pF Units CL
VCC Symbol Parameter
VCC
16 Outputs Switching (Note 11) Max tOSHL (Note 13) tOSLH (Note 13) tPS (Note 14) tOST (Note 13) tPV (Note 15) Pin to Pin Skew HL Transitions Pin to Pin Skew LH Transitions Duty Cycle LH-HL Skew Pin to Pin Skew LH/HL Transitions Device to Device Skew LH/HL Transitions 1.0 1.0 1.5 1.7 2.0
16 Outputs Switching (Note 12) Max 1.5 1.5 1.5 2.0 2.5 ns ns ns ns ns
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). The specification is guaranteed but not tested. Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested.
Capacitance
Symbol CIN COUT (Note 16) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0
1 MHz; per MIL STD-883, Method 3012.
Units pF pF
Conditions TA VCC VCC 25qC 5.0V 5.0V
Note 16: COUT is measured at frequency f
5
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74ABT16541
AC Loading
* Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load Amplitude 3.0V Rep Rate 1 MHz tW 500 ns
FIGURE 2. Test Input Pulse Requirements tr 2.5 ns tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT16541
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74ABT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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